Free Area Estimator for Simulated Annealing of VLSI Floor Plans

Ashwini Baligatti , Ashwini Desai, Dr. Uday Wali

VLSI floor planning problem encounter large dynamically changing decision trees and is known to be a NP Hard problem. Near optimal results can be obtained by non-deterministic methods such as simulated annealing. Annealing can be simulated as a stochastic process with several known and un-known variables in the process. Estimation of area for movement of individual modules at a given temperature depends on many physical parameters assigned to individual modules. In such a scenario, estimating free area within which a module can move at a given temperature is the prime factor that decides behavior of simulated annealing. We have implemented a new ‘free area estimator’ that helps improve performance of simulated annealing algorithms. Some of the simulation results have been reported.