This paper proposes a modification of the pre-processing stage of the Pan-Tompkins algorithm. In this paper, the fractional order differentiator now stands in for the integer order differentiator. Since the gain of the fractional order differentiator is lesser than its integer-order counterpart, the amplification of the high-frequency noise is reduced thus making the design robust to noise. Moreover, all the circuits in this design have been implemented using low-power design techniques so that the system can work with extremely low power consumption. The achievement of the advanced design has been validated by simulations carried out in the HSPICE EDA tool using the TMSC CMOS 130nm process.