Indexing Metadata

1 Title of the Article Free Area Estimator for Simulated Annealing of VLSI Floor Plans
2 Author's name Ashwini Baligatti: Electronics and Communication, KLE Dr. MSSCET, Belgaum, India, 9986882865, ashwini.baligatti@gmail.com
3 Author's name Ashwini Desai, Dr. Uday Wali
4 Subject Electronics and Communication
5 Keyword(s) Floorplan, Simulated Annealing, Temperature, Free area estimation
6 Abstract

VLSI floor planning problem encounter large dynamically changing decision trees and is known to be a NP Hard problem. Near optimal results can be obtained by non-deterministic methods such as simulated annealing. Annealing can be simulated as a stochastic process with several known and un-known variables in the process. Estimation of area for movement of individual modules at a given temperature depends on many physical parameters assigned to individual modules. In such a scenario, estimating free area within which a module can move at a given temperature is the prime factor that decides behavior of simulated annealing. We have implemented a new ‘free area estimator’ that helps improve performance of simulated annealing algorithms. Some of the simulation results have been reported.

7 Publisher Innovative Research Publication
8 Journal Name; vol., no. International Journal of Innovative Research in Computer Science & Technology (IJIRCST); Volume-2 Issue-4
9 Publication Date July 2014
10 Type Peer-reviewed Article
11 Format PDF
12 Uniform Resource Identifier https://ijircst.org/view_abstract.php?title=Free-Area-Estimator-for-Simulated-Annealing-of-VLSI-Floor-Plans&year=2014&vol=2&primary=QVJULTg4
13 Digital Object Identifier(DOI)  
14 Language English
15 Page No 52-55