Volume- 2
Issue- 1
Year- 2014
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Mohassin Ahmad , Abdul Gaffar Mir, Najeeb-ud-din Hakim
Digital image processing (DIP) is an ever growing area with a variety of applications including medicine, video surveillance, and many more. In order to improve the performance of DIP systems image processing algorithms are implemented in hardware instead of software. The idea here is mainly to obtain a system faster than software image processing. Image processing tasks such as filtering, stereo correspondence and feature detection are inherently highly parallelizable. Thus FPGAs (Field Programmable Gate Arrays) can be a useful approach in the area of Digital Signal Processing. FPGAs provide advantage of the parallelism, low cost, and low power consumption. They are semiconductor devices that contain a number of logic blocks, which can be programmed to perform anything from basic digital gate level techniques, to complex image processing
algorithms. This paper provides an overview of the various works that demonstrate the benefits of using FPGAs to implement image
processing algorithms like median filter, morphological, convolution, smoothing operation and edge detection, etc. Gray-level images are
very common in image processing. These types of images use eight bits to code each pixel value, which results in 256 different possible
shades of grey, ranging from 0 (black value) to 255 (white value). Latest generations FPGAs compute more than 160 billion multiplication and accumulation (MAC) operations per second.
C. T. Johnston, K. T. Gribbon, D. G. Bailey , “ Implementing Image Processing Algorithms on FPGAs,” Proceedings of the Image and Vision Computing New Zealand Conference 2003, Massey University, Palmerston North, New Zealand, pp. 408-413, Nov. 2003.
Cesar Torres-Huitzil, Miguel Arias-Estrada, “ FPGA-Based Configurable Systolic Architecture For Window-Based Image Processing,” EURASIP Journal on Applied Signal Processing, Vol. 7, ISSN:1024–1034, 2005
Haiqian Yu, Miriam Leeser, “ Automatic Sliding Window Operation Optimization for FPGA- Based Computing Board,” 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2006.
Donald G Bailey, “ Image Border Management for FPGA Based Filters,”Sixth IEEE International Symposium on Electronic Design, Test and Application, 2011.
Nelson, “ A Further Study of Image Processing Techniques on FPGA Hardware,” Independent Study Pape r, May 2000.
Madhuri Gundam, Dimitrios Charalampidis, “ Median Filter on FPGAs,” 44th IEEE Southeastern Symposium on System Theory , University of North Florida, Jacksonville, FL March 11-13, 2012.
Elmoncef Benrhouma, Meddeb Souad, Abdulqadir Alaqeeli, Hamid Amiri, “ Study and Design of Median Filter,” SIDOP 2nd Workshop on Signal and Document Processing, 2012.
R.Arunmozhi, G.Mohan, “ Implementation of Digital Image Morphological Algorithm on FPGA using Hardware Description Languages,” International Journal of Computer Applications, Vol. 57, No.5, pp 0975 – 8887, Nov. 2012.
Stephanie Parker, J. Kemi Ladeji-Osias, “ Implementing Histogram Equalization Algorithm in Reconfigurable Hardware,” July 30, 2009.
N Otsu, “ A Threshold Selection Method from Gray-Level Histogram,” IEEE Transactions on Systems, Man, and Cybernetics, Vol. 9, N0. 1, 1979, pp.62-66.
Sudeep K C and Dr. Jharna Majumdar, “ A Novel Architecture for Real Time Implementation of Edge Detectors on FPGA,” International Journal of Computer Science Issues, Vol. 8, Issue 1, January 2011
G. Anusha, Dr.T. Jaya Chandra Prasad, Dr..D. Satya Narayana, “Implementation of SOBEL Edge Detection on FPGA,” International
Journal of Computer Trends and Technology, Vol. 3, Issue 3, 2012
C. Sanchez-Ferreira, J. Y. Mori, C. H. Llanos, “ Background Subtraction Algorithm for Moving Object Detection in FPGA,” Proceedings of the 2012 IEEE Southern Conference on Programmable Logic (SPL),2012
Daggu Venkateshwar Rao, Shruti Patil, Naveen Anne Babu and V Muthukumar, “ Implementation and Evaluation of Image Processing Algorithms on Reconfigurable Architecture using C-based Hardware Descriptive Languages,” International Journal of Theoretical and Applied Computer Sciences, Vol. 1, No. 1, 2006.
Research Scholar, Department of ECE, National Institute of Technology, Srinagar, J & K, India (e-mail: mohassin623@gamil.com).
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