International Journal of Innovative Research in Computer Science and Technology
Year: 2014, Volume: 2, Issue: 1
First page : ( 43) Last page : ( 45)
Online ISSN : 2350-0557.
K. A. Deshmukh , Prof. P. R. Indurkar, Prof. Mrs. D. M. Khatri
A high performance hardware FFT have numerous application in instrumentation and communication systems. It describes new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm knows to have lower multiplicative complexity than both radix-2 as well as radix-4 algorithm. The split-radix algorithm maps onto a constant geometry interconnect structure in which the wiring in each FFT stage is indistinguishable, resulting in low multiplexing overhead. We are exploiting the lower arithmetic complexity of split-radix to lower dynamic energy, by gating the multipliers during trivial multiplication. The proposed FFT accomplishes less power than a parallel radix-4 design when computing at some point, the real-valued transform.
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Student, M. Tech, Department of electronics and telecommunication Engg, BDCOE, Sewagram (wardha) Maharashtra, India, 09960559366, (e-mail deshmukhkarishma589@gmail.com)
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Ms. Prajakta Ananda Kharote., Prof. M. P. Satone, .
May 2014 - Vol 2, Issue 3
